Konstantis Daloukas, Nestor Evmorfopoulos
Presented herein are systems, methods, and devices for analyzing a circuit. A netlist is
obtained and parsed, where the netlist describes the circuit having one or more branches
and one or more nodes. A linear system describing the circuit is obtained and compressed
using a hierarchical approach. Compression involves storing off-diagonal sub-blocks in a
dense matrix in a low-rank format to reduce the density of the matrix. The linear system is
then solved using an iterative operation. An initial guess is used for the voltage at each Iterative Solution Using Compressed Inductive Matrix for Efficient Simulation of Very-Large Scale Circuits
US 15/145,611

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