We conduct research for studying and addressing the effects of process variation, which will be more profound in forthcoming nano-scale circuits, either at architectural or physical level. To that end, in cooperation with the Telecommunication Circuits Laboratory (TCL) and Dr. Georgios Karakonstantis from EPFL, we design and develop simulation methodologies for modeling process variation in significant IC components (such as memory blocks) and process variation-aware algorithms that can be integrated in custom IC design flows .
We work on parallel algorithms that harness the potential of emerging parallel architectures to accelerate VLSI EDA tools for large-scale VLSI designs.
Who we are
The VLSI and EDA Tools (VEDA) Laboratory is part of the Department of Electrical and Computer Engineering at University of Thessaly. The VEDA Lab focuses on addressing the challenges presented by the rapid increase in size and complexity of the integrated circuits.It explores methodologies and techniques for the development of algorithms and techniques for Electronic Design Automation (EDA) tools that target the modeling, simulation, optimization and verification of low-power, deep-submicron VLSI circuits.